Bingyi Zhang

I am an AI developer technology engineer at NVIDIA. I received my Ph.D. in Computer Engineering from the University of Southern California, where I was advised by Professor Viktor K. Prasanna in the FPGA/Parallel Computing Lab. My research interests span high-performance computing, compiler design, computer architecture, reconfigurable computing, and graph machine learning.

Prior to USC, I earned my M.S. from the State Key Laboratory of ASIC and System at Fudan University, under the guidance of Professor Jun Han and Professor Xiaoyang Zeng.

Ph.D. Thesis: Hardware-Software Codesign for Accelerating Graph Neural Networks on FPGA

Professional Service: I have served as a reviewer over 80 times for journals and conferences, including:

Journals (70+): IEEE TVLSI, IEEE TIP, IET Computer Vision, IET Image Processing, Neurocomputing, Engineering Applications of Artificial Intelligence, Information Sciences, and others.
Conferences (10+): ASICON 2021, ICSICT 2022, IEEE International Radar Conference 2023.

news

Jan 15, 2025	Our paper “Model-Architecture Codesign for High-Performance and Energy-Efficient SAR ATR on FPGA” is accepted by IEEE Transactions on Geoscience and Remote Sensing (TGRS)
Dec 15, 2024	Our paper “ViTeGNN: Towards Versatile Inference of Temporal Graph Neural Networks on FPGA” is accepted by IEEE Transactions on Parallel and Distributed Systems (TPDS)
Sep 15, 2024	Our paper “VisionAGILE: A Versatile Domain-Specific Accelerator for Computer Vision Tasks” is accepted by IEEE Transactions on Parallel and Distributed Systems (TPDS)
Feb 15, 2024	Our paper “GCV-Turbo: End-to-end Acceleration of GNN-based Computer Vision Tasks on FPGA” is accepted by 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2024)
Feb 1, 2024	Our paper “HitGNN: High-Throughput GNN Training Framework on CPU+Multi-FPGA Heterogeneous Platform” is accepted by IEEE Transactions on Parallel and Distributed Systems (TPDS)