publications

2024

1. TPDS

   HitGNN: High-Throughput GNN Training Framework on CPU+Multi-FPGA Heterogeneous Platform

   Yi-Chien Lin, Bingyi Zhang, and Viktor K. Prasanna

   IEEE Transactions on Parallel and Distributed Systems, 2024
2. FCCM

   GCV-Turbo: End-to-end Acceleration of GNN-based Computer Vision Tasks on FPGA

   Bingyi Zhang, Rajgopal Kannan, Carl Busart, and 1 more author

   In 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2024
3. FCCM

   Accelerating ViT Inference on FPGA through Static and Dynamic Pruning

   Dhruv Parikh, Shouyi Li, Bingyi Zhang, and 3 more authors

   In 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2024
4. SPIE

   VTR: an optimized vision transformer for SAR ATR acceleration on FPGA

   Sachini Wickramasinghe, Dhruv Parikh, Bingyi Zhang, and 3 more authors

   In Image Sensing Technologies: Materials, Devices, Systems, and Applications XI, 2024
5. TPDS

   VisionAGILE: A Versatile Domain-Specific Accelerator for Computer Vision Tasks

   Bingyi Zhang, Rajgopal Kannan, Carl Busart, and 1 more author

   IEEE Transactions on Parallel and Distributed Systems, 2024
6. ICIP

   A Single Graph Convolution is All You Need: Efficient Grayscale Image Classification

   Jacob Fein-Ashley, Sachini Wickramasinghe, Bingyi Zhang, and 2 more authors

   In 2024 IEEE International Conference on Image Processing (ICIP), 2024
7. Ph.D. Thesis

   Hardware-Software Codesign for Accelerating Graph Neural Networks on FPGA

   Bingyi Zhang

   2024

   Copyright - Database copyright ProQuest LLC; ProQuest does not claim copyright in the individual underlying works; Last updated - 2024-09-08

   Abs

   Graph Neural Networks (GNNs) have revolutionized many real-world applications where data can be represented as graphs. These applications include recommendation systems, social networks, traffic prediction, computer vision tasks (e.g., the tasks in autonomous driving), etc. Many applications require high-performance execution (e.g., low latency or high throughput) of GNNs. To this end, several state-of-the-art libraries (e.g., PyTorch Geometric and Deep Graph Library) have been developed for executing GNNs on general-purpose processors, including CPUs and GPGPUs. However, current GNN libraries on general-purpose processors achieve sub-optimal performance due to several challenges: 1. Irregular data structures: graphs in real-world applications are highly unstructured, with uneven degree distribution. Such irregularity leads to complex data access patterns. 2. Heterogeneous computation kernels: GNNs involve both sparse computation kernels (e.g., sparse-dense matrix multiplication) and dense computation kernels (dense-dense matrix multiplication). While general-purpose processors are efficient for dense computations, their data path and memory hierarchy are inefficient for sparse computations. 3. Dynamic data sparsity: In many applications, the graph connectivity and the data sparsity of vertex features are unknown before executing the GNN model. Therefore, a GNN system needs to deal with the data sparsity of the graphs dynamically. Such dynamic data sparsity makes it difficult for the compiler and runtime system to generate an optimal execution scheme for GNNs. 4. Mixture of models: Some GNN-based applications use the combined strength of different machine learning models. For example, GNN-based computer vision tasks utilize a mixture of convolutional neural networks (CNNs) and GNN models. Such a combination leads to complex data flow.In this dissertation, we address the above challenges through novel hardware-software codesigns on Field Programmable Gate Array (FPGA). First, to address the challenges of irregular data structures and heterogeneous computation kernels, we develop a hardware-software codesign on FPGA for GNN inference, named GraphAGILE. GraphAGILE incorporates a compiler and an accelerator design on FPGA. For a given input GNN model and an input graph, the compiler translates them into the intermediate representation (IR). Then, the compiler performs several compiler optimizations and generates a sequence of instructions for hardware execution. The hardware accelerator on FPGA executes various computation kernels through flexible customized data paths and memory organization. Second, we propose Dynasparse, an efficient codesign of runtime system and hardware to exploit the dynamic sparsity in GNN inference. The hardware design of Dynasparse has a flexible data path to execute the computation kernels of various data sparsity. The runtime system utilizes a theoretical performance model to dynamically map a GNN computation kernel to the computation primitive based on data sparsity. Third, we propose GCV-Turbo, a hardware-software codesign accelerating GNN-based computer vision (CV) tasks. GNN-based CV tasks involve a mixture of GNN layers and CNN layers. To this end, GCV-Turbo incorporates novel compiler optimizations to orchestrate the dataflow of two types of models. GCV-Turbo further incorporates novel hardware mechanisms to facilitate efficient data layout transformation between different layers. Our implementations based on our codesign methodology achieve superior performance on various GNN-based applications.

2023

1. IPDPS

   Dynasparse: Accelerating GNN Inference through Dynamic Sparsity Exploitation

   Bingyi Zhang, and Viktor Prasanna

   2023 International Parallel and Distributed Processing Symposium, 2023

   arXiv
2. GEOProcessing

   Graph Neural Network for Accurate and Low-complexity SAR ATR

   Bingyi Zhang, Sasindu Wijeratne, Rajgopal Kannan, and 2 more authors

   2023

   arXiv
3. TPDS

   GraphAGILE: An FPGA-based Overlay Accelerator for Low-latency GNN Inference

   Bingyi Zhang, Hanqing Zeng, and Viktor Prasanna

   IEEE Transactions on Parallel and Distributed Systems, 2023

   arXiv
4. SPIE

   PAHD: perception-action based human decision making using explainable graph neural networks on SAR images

   Sasindu Wijeratne, Bingyi Zhang, Rajgopal Kannan, and 2 more authors

   In Automatic Target Recognition XXXIII, 2023
5. SPIE

   Graph neural network based SAR automatic target recognition with human-in-the-loop

   Bingyi Zhang, Sasindu Wijeratne, Rajgopal Kannan, and 2 more authors

   In Algorithms for Synthetic Aperture Radar Imagery XXX, 2023
6. FPL

   Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration

   Paul Chen, Pavan Manjunath, Sasindu Wijeratne, and 2 more authors

   33rd International Conference on Field-Programmable Logic and Applications, 2023

   arXiv
7. RADAR

   How can Human-in-the-loop Improve the Performance of SAR ATR? A Reinforcement Learning Based Approach

   Bingyi Zhang, Sasindu Wijeratne, Tian Ye, and 4 more authors

   In 2023 IEEE International Radar Conference (RADAR), 2023
8. HPEC

   Performance of Graph Neural Networks for Point Cloud Applications

   Dhruv Parikh, Bingyi Zhang, Rajgopal Kannan, and 2 more authors

   In 2023 IEEE High Performance Extreme Computing Conference (HPEC), 2023
9. HPEC

   Accelerating GNN-Based SAR Automatic Target Recognition on HBM-Enabled FPGA

   Bingyi Zhang, Rajgopal Kannan, Viktor Prasanna, and 1 more author

   In 2023 IEEE High Performance Extreme Computing Conference (HPEC), 2023

2022

1. FPGA

   HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform

   Yi-Chien Lin, Bingyi Zhang, and Viktor Prasanna

   In Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2022
2. IPDPS

   Model-Architecture Co-Design for High Performance Temporal GNN Inference on FPGA

   Hongkuan Zhou, Bingyi Zhang, Rajgopal Kannan, and 2 more authors

   In 2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2022

   arXiv
3. HPEC

   Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA

   Sasindu Wijeratne, Akhilesh Jaiswal, Ajey P Jacob, and 2 more authors

   In 2022 IEEE High Performance Extreme Computing Conference (HPEC), 2022
4. HiPC

   Low-latency mini-batch gnn inference on cpu-fpga heterogeneous platform

   Bingyi Zhang, Hanqing Zeng, and Viktor Prasanna

   arXiv preprint arXiv:2206.08536, 2022
5. FPL

   Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGA

   Bingyi Zhang, Rajgopal Kannan, Viktor Prasanna, and 1 more author

   arXiv preprint arXiv:2301.01454, 2022

   arXiv PDF
6. ICFPT

   Hypersort: High-performance Parallel Sorting on HBM-enabled FPGA

   Soundarya Jayaraman, Bingyi Zhang, and Viktor Prasanna

   In 2022 International Conference on Field-Programmable Technology (ICFPT), 2022
7. HPEC

   Modeling the Energy Efficiency of GEMM using Optical Random Access Memory

   Bingyi Zhang, Akhilesh Jaiswal, Clynn Mathew, and 4 more authors

   In 2022 IEEE High Performance Extreme Computing Conference (HPEC), 2022
8. CARLA

   Accelerating GNN Training on CPU $+ $ Multi-FPGA Heterogeneous Platform

   Yi-Chien Lin, Bingyi Zhang, and Viktor Prasanna

   In Latin American High Performance Computing Conference, 2022

2021

1. FCCM

   BoostGCN: A framework for optimizing GCN inference on FPGA

   Bingyi Zhang, Rajgopal Kannan, and Viktor Prasanna

   In 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021
2. HPEC

   GCN Inference Acceleration using High-Level Synthesis

   Yi Chien Lin, Bingyi Zhang, and Viktor Prasanna

   In 2021 IEEE High Performance Extreme Computing Conference (HPEC), 2021
3. HPEC

   Efficient Neighbor-Sampling-based GNN Training on CPU-FPGA Heterogeneous Platform

   Bingyi Zhang, Sanmukh R Kuppannagari, Rajgopal Kannan, and 1 more author

   In 2021 IEEE High Performance Extreme Computing Conference (HPEC), 2021

   Code
4. HiPC

   Performance of Local Push Algorithms for Personalized PageRank on Multi-core Platforms

   Madhav Aggarwal, Bingyi Zhang, and Viktor Prasanna

   In 2021 IEEE 28th International Conference on High Performance Computing, Data, and Analytics (HiPC), 2021

2020

1. ASAP

   Hardware acceleration of large scale gcn inference

   Bingyi Zhang, Hanqing Zeng, and Viktor Prasanna

   In 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2020

   Code
2. FCCM

   Accelerating large scale GCN inference on FPGA

   Bingyi Zhang, Hanqing Zeng, and Viktor Prasanna

   In 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2020

2019

1. TCAS II

   A real-time and hardware-efficient processor for skeleton-based action recognition with lightweight convolutional neural network

   Bingyi Zhang, Jun Han, Zhize Huang, and 2 more authors

   IEEE Transactions on Circuits and Systems II: Express Briefs, 2019
2. BioCAS

   A skeleton-based action recognition system for medical condition detection

   Jun Yin, Jun Han, Chenghao Wang, and 2 more authors

   In 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2019

2018

1. DSP

   MiniTracker: a lightweight CNN-based system for visual object tracking on embedded device

   Bingyi Zhang, Xin Li, Jun Han, and 1 more author

   In 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP), 2018